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HD74HC194
4-bit Bidirectional Universal Shift Register
REJ03D0589-0200 (Previous ADE-205-466) Rev.2.00 Jan 31, 2006
Description
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control inputs, and a direct overriding clear line. The register has four distinct modes of operation: parallel (broadside) load, shift right (in the direction QA toware QD); shift left; inhibit clock (do nothing). Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into their respective flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift left serial input. Clocking of the flip-flops is inhibited when both mode control inputs are low. The mode control inputs should be changed only when the clock input is high.
Features
* * * * * * High Speed Operation: tpd (Clock to Q) = 12 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max Ordering Information
Part Name HD74HC194P Package Type DILP-16 pin Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Abbreviation P -- Taping Abbreviation (Quantity)
Rev.2.00 Jan 31, 2006 page 1 of 8
HD74HC194
Function Table
Operating Mode Clear Parallel load Shift right Shift left Hold Clear L H H H H H H H H Mode S0 S1 X X H H L H L H H L H L L L X X X X Inputs Serial Clock Shift Left Shift Right X X X X X X H X L H X L X X L H X X X X X X Parallel B C X X b c X X X X X X X X X X X X X X Outputs D X d X X X X X X X QA L a H L QBn QBn QA0 QA0 QA0 QB L b QAn QAn QCn QCn QB0 QB0 QB0 QC L c QBn QBn QDn QDn QC0 QC0 QC0 QD L d QCn QCn H L QD0 QD0 QD0
A X a X X X X X X X
H: L: X: :
high level (Steady state) low level (Steady state) don't care transition from low to high level.
a, b, c, d : the level of steady-state input at inputs A, B, C or D respectively. QA0, QB0, QC0, QD0 : the level of QA, QB, QC or QD respectively, before the indicated steady-state input conditions were established. QAn, QBn, QCn, QDn : the level of QA, QB, QC or QD respectively before the most recent transition of the clock.
Pin Arrangement
Clear 1 Shift Right Serial-Input 2 R A B C D L CLR QA QB QC QD CK S1
16 VCC 15 QA 14 QB Parallel 13 QC Outputs 12 QD 11 Clock 10 S1 Mode Control 9 S0 (Top view)
A3 B4 Parallel Inputs C5 D6 Shift Left Serial-Input 7
S0
GND 8
Rev.2.00 Jan 31, 2006 page 2 of 8
HD74HC194
Timing Diagram
Clock Mode Control Inputs S0 S1 Clear Serial Data Inputs R L A Parallel Data Inputs B C D QA QB Outputs QC QD Shift Right Clear Load Shift Left Inhibit Clear H L H L
Logic Diagram
Serial Shift Left Serial Shift Right
D
C
B
A
S0
S1
D C CQ CL CL
D C CQ CL CL
D C CQ CL CL
D C CQ CL CL
Clock Clear
QD
QC
QB
QA
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 25 50 500 -65 to +150 Unit V V mA mA mA mW
C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Rev.2.00 Jan 31, 2006 page 3 of 8
HD74HC194
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400 Unit V V Conditions
C
ns VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Ta = 25C Min Typ Max 1.5 -- -- 3.15 -- -- 4.2 -- -- -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to+85C Unit Min Max 1.5 -- V 3.15 -- 4.2 -- -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40 V Test Conditions
VIL
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
VOL
V
Vin = VIH or VIL
IOH = -4 mA IOH = -5.2 mA IOL = 20 A
Input current Quiescent supply current
Iin ICC
IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Rev.2.00 Jan 31, 2006 page 4 of 8
HD74HC194
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Hold time th 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Min -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 100 20 17 150 30 25 0 0 0 25 5 4 -- -- -- -- Ta = 25C Ta = -40 to +85C Unit Test Conditions Typ Max Min Max -- 6 -- 5 ns -- 30 -- 24 -- 35 -- 28 -- 140 -- 175 ns Clock to Q 12 28 -- 35 -- 24 -- 30 -- 140 -- 175 ns 12 28 -- 35 -- 24 -- 30 -- 150 -- 190 ns Clear to Q 13 30 -- 38 -- 26 -- 33 -- -- 100 -- ns Clock or Clear 6 -- 20 -- -- -- 17 -- -- -- 125 -- ns A, B, C or D to Clock 7 -- -- 17 -- -- -4 -- -- 1 -- -- 5 -- 5 -- -- -- -- -- -- -- -- -- -- -- 75 15 13 10 25 21 187 37 31 0 0 0 31 6 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 95 19 16 10
tPHL
tPLH
tPHL
Pulse width
tw
Setup time
tsu
ns
Mode controls to Clock
ns
Any input
Removal time
trem
ns
Clear inactive to Clock
Output rise/fall time Input capacitance
tTLH tTHL Cin
ns
pF
Rev.2.00 Jan 31, 2006 page 5 of 8
HD74HC194
Test Circuit
VCC VCC Output QA Output QB CL = 50 pF
Input Pulse Generator Zout = 50
Clear Clock S0 S1 R L A B C D
See Function Table
Output CL = 50 pF
QC Output CL = 50 pF QD CL = 50 pF
Note : 1. CL includes probe and jig capacitance.
Rev.2.00 Jan 31, 2006 page 6 of 8
HD74HC194
Waveforms
* Waveform - 1
tn tr Clock tsu
50%
tn+1 tf
tn
tn+1
VCC
50%
th
tsu
th
0V VCC
L or R
50%
50%
50%
50%
0V tPLH
50%
tPHL VOH
50%
Q
VOL
Notes : 1. For right shift, measure QA at tn+1, QB at tn+2, QC at tn+3, QD at tn+4, respectively. For left shift, measure QA at tn+4, QB at tn+3, QC at tn+2, QD at tn+1, respectively. 2. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns
* Waveform - 2
tr
90 %
tf VCC
10 %
Clock
10 %
50 % 50 %
tw
0V
tf
90 % 50 % 10 %
VOH VOL
Clear
t PHL VOH Q
50 % 10 %
VOL
t THL Note : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns
Rev.2.00 Jan 31, 2006 page 7 of 8
HD74HC194
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
Rev.2.00 Jan 31, 2006 page 8 of 8
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